/**
 * @file    gt9881_sysctrl.h
 * 
 * @author  Giantec-Semi ATE
 * @brief CMSIS GT98xx Device Peripheral Access Layer Header File
 * @version 0.1
 * 
 * @copyright Copyright (c) 2021 Giantec-Semi
 * 
 */

#ifndef GT98XX_DEVICE_GT9881_SYSCTRL_H_
#define GT98XX_DEVICE_GT9881_SYSCTRL_H_

#ifdef __cplusplus
  extern "C" {
#endif /* __cplusplus */

#include "gt9881.h"

/**
 
 * @addtogroup Peripheral_Registers_Structures
 * @{
 */

/**
 * @struct RstCtlRegTypedef
 * @brief  MCU Reset Control Registers structure definition
 */
typedef struct tagRstCtlRegTypedef {
  __IO uint32_t GLOBAL_SOFT_RST;    ///< Software global reset
  __IO uint32_t MCU_BLK_RST;        ///< MCU module block
  __IO uint32_t EFLASH_REMAP_RST;   ///< EFlash remap reset
} RstCtlRegTypedef;

/**
 * @struct FuncAuxRegTypedef
 * @brief  MCU Functionality Auxiliary Registers structure definition
 */
typedef struct tagFuncAuxRegTypedef {
  __IO uint32_t MCU_MODE_CTL;       ///< MCU mode control
  __IO uint32_t EXT_INT_CTL;        ///< external interrupt control
  __IO uint32_t DGB_SIG_OEN_CTL;    ///< debug signal control
} FuncAuxRegTypedef;

/**
 * @struct McuAuxDbgTypedef
 * @brief  MCU Auxiliary Debug Registers structure definition
 */
typedef struct tagMcuAuxDbgTypedef {
  __IO uint32_t MCU_AUX_DBG0;       ///< It is an auxiliary register for SW to use for debug information record
  __IO uint32_t MCU_AUX_DBG1;       ///< It is an auxiliary register for SW to use for debug information record
  __IO uint32_t MCU_AUX_DBG2;       ///< It is an auxiliary register for SW to use for debug information record
} McuAuxDbgTypedef;

/** @} Peripheral_Registers_Structures */

/**
 * @addtogroup Peripheral_Memory_Map
 * @{
 */
#define RCC_BASE                        (PERIPH_BASE + 0x0000UL)      ///< Rcc base address
#define RST_CTL_REG_BASE                (RCC_BASE + 0x20UL)           ///< MCU Reset Control Registers base address
#define MCU_CHIP_ID                     (RCC_BASE + 0x40UL)           ///< Chip ID Register
#define FUNC_AUX_REG_BASE               (RCC_BASE + 0x50UL)           ///< MCU Functionality Auxiliary Registers base address
#define BOOT_STATUS                     (RCC_BASE + 0x60UL)           ///< MCU Reset Status Register
#define MCU_AUX_DBG_BASE                (RCC_BASE + 0x120UL)          ///< MCU Auxiliary Debug Registers base address
/** @} Peripheral_Memory_Map */

/**
 * @addtogroup Peripheral_Declaration
 * @{
 */
#define RST_CTL_REG               ((RstCtlRegTypedef*)RST_CTL_REG_BASE)
///< MCU Reset Control Registers operator
#define FUNC_AUX_REG              ((FuncAuxRegTypedef*)FUNC_AUX_REG_BASE)
///< MCU Functionality Auxiliary Registers operator
#define MCU_AUX_DBG               ((McuAuxDbgTypedef*)MCU_AUX_DBG_BASE)
///< MCU Auxiliary Debug Registers
/** @} Peripheral_Declaration */

/**
 * @defgroup SYSREG System Registers
 * @ingroup  Peripheral_Registers_Bits_Definition
 * @brief    System Registers
 * @{
 */

/**
 * @defgroup RESET_CONTROL MCU Reset Control Registers
 * @ingroup  SYSREG
 * @brief    MCU Reset Control Registers
 * @{
 */

/**
 * @defgroup RESET_CONTROL_BITMAP MCU Reset Bitmap
 * @ingroup  RESET_CONTROL
 * @brief    Bitmap of MCU Reset Control Registers
 * @{
 */

#define GLOBAL_SOFT_RST_Pos                     (0U)    ///< Poision of GLOBAL_SOFT_RST
#define GLOBAL_SOFT_RST_Msk                     (0xFFFFFFFFUL << GLOBAL_SOFT_RST_Pos)    ///< Bitmask of GLOBAL_SOFT_RST
/**
 * @def   GLOBAL_SOFT_RST
 * @brief Resets whole MCU system except clock generate and related control registers
 * <pre>
 * @a 8'hAA55A5A5 : global Reset.
 * @a Other       : no effect
 * </pre>
 */
#define GLOBAL_SOFT_RST                         GLOBAL_SOFT_RST_Msk

#define MCU_BLK_RST_DMA_Pos                     (0U)    ///< Poision of MCU_BLK_RST_DMA
#define MCU_BLK_RST_DMA_Msk                     (0x1UL << MCU_BLK_RST_DMA_Pos)    ///< Bitmask of MCU_BLK_RST_DMA
/**
 * @def   MCU_BLK_RST_DMA
 * @brief DMA module reset.
 * <pre>
 * @a 1'b0 : Reset
 * @a 1'b1 : Release
 * </pre>
 */
#define MCU_BLK_RST_DMA                         MCU_BLK_RST_DMA_Msk

#define MCU_BLK_RST_UART_Pos                    (5U)    ///< Poision of MCU_BLK_RST_UART
#define MCU_BLK_RST_UART_Msk                    (0x1UL << MCU_BLK_RST_UART_Pos)    ///< Bitmask of MCU_BLK_RST_UART
/**
 * @def   MCU_BLK_RST_UART
 * @brief UART module reset.
 * <pre>
 * @a 1'b0 : Reset
 * @a 1'b1 : Release
 * </pre>
 */
#define MCU_BLK_RST_UART                        MCU_BLK_RST_UART_Msk

#define MCU_BLK_RST_SPI1_Pos                    (6U)    ///< Poision of MCU_BLK_RST_SPI1
#define MCU_BLK_RST_SPI1_Msk                    (0x1UL << MCU_BLK_RST_SPI1_Pos)    ///< Bitmask of MCU_BLK_RST_SPI1
/**
 * @def   MCU_BLK_RST_SPI1
 * @brief SPI1 module reset.
 * <pre>
 * @a 1'b0 : Reset
 * @a 1'b1 : Release
 * </pre>
 */
#define MCU_BLK_RST_SPI1                        MCU_BLK_RST_SPI1_Msk

#define MCU_BLK_RST_SPI2_Pos                    (7U)    ///< Poision of MCU_BLK_RST_SPI2
#define MCU_BLK_RST_SPI2_Msk                    (0x1UL << MCU_BLK_RST_SPI2_Pos)    ///< Bitmask of MCU_BLK_RST_SPI2
/**
 * @def   MCU_BLK_RST_SPI2
 * @brief SPI2 module reset.
 * <pre>
 * @a 1'b0 : Reset
 * @a 1'b1 : Release
 * </pre>
 */
#define MCU_BLK_RST_SPI2                        MCU_BLK_RST_SPI2_Msk

#define MCU_BLK_RST_I2C1_Pos                    (8U)    ///< Poision of MCU_BLK_RST_I2C1
#define MCU_BLK_RST_I2C1_Msk                    (0x1UL << MCU_BLK_RST_I2C1_Pos)    ///< Bitmask of MCU_BLK_RST_I2C1
/**
 * @def   MCU_BLK_RST_I2C1
 * @brief I2C1 module reset.
 * <pre>
 * @a 1'b0 : Reset
 * @a 1'b1 : Release
 * </pre>
 */
#define MCU_BLK_RST_I2C1                        MCU_BLK_RST_I2C1_Msk

#define MCU_BLK_RST_I2C2_Pos                    (9U)    ///< Poision of MCU_BLK_RST_I2C2
#define MCU_BLK_RST_I2C2_Msk                    (0x1UL << MCU_BLK_RST_I2C2_Pos)    ///< Bitmask of MCU_BLK_RST_I2C2
/**
 * @def   MCU_BLK_RST_I2C2
 * @brief I2C2 module reset.
 * <pre>
 * @a 1'b0 : Reset
 * @a 1'b1 : Release
 * </pre>
 */
#define MCU_BLK_RST_I2C2                        MCU_BLK_RST_I2C2_Msk

#define MCU_BLK_RST_IWDT_Pos                    (10U)    ///< Poision of MCU_BLK_RST_IWDT
#define MCU_BLK_RST_IWDT_Msk                    (0x1UL << MCU_BLK_RST_IWDT_Pos)    ///< Bitmask of MCU_BLK_RST_IWDT
/**
 * @def   MCU_BLK_RST_IWDT
 * @brief IWDT module reset.
 * <pre>
 * @a 1'b0 : Reset
 * @a 1'b1 : Release
 * </pre>
 */
#define MCU_BLK_RST_IWDT                        MCU_BLK_RST_IWDT_Msk

#define MCU_BLK_RST_TIMER_Pos                   (11U)    ///< Poision of MCU_BLK_RST_TIMER
#define MCU_BLK_RST_TIMER_Msk                   (0x1UL << MCU_BLK_RST_TIMER_Pos)    ///< Bitmask of MCU_BLK_RST_TIMER
/**
 * @def   MCU_BLK_RST_TIMER
 * @brief TIMER module reset.
 * <pre>
 * @a 1'b0 : Reset
 * @a 1'b1 : Release
 * </pre>
 */
#define MCU_BLK_RST_TIMER                       MCU_BLK_RST_TIMER_Msk

#define MCU_BLK_RST_GPIO_Pos                    (12U)    ///< Poision of MCU_BLK_RST_GPIO
#define MCU_BLK_RST_GPIO_Msk                    (0x1UL << MCU_BLK_RST_GPIO_Pos)    ///< Bitmask of MCU_BLK_RST_GPIO
/**
 * @def   MCU_BLK_RST_GPIO
 * @brief GPIO module reset.
 * <pre>
 * @a 1'b0 : Reset
 * @a 1'b1 : Release
 * </pre>
 */
#define MCU_BLK_RST_GPIO                        MCU_BLK_RST_GPIO_Msk

#define MCU_BLK_RST_RINGBUFFER_Pos              (13U)    ///< Poision of MCU_BLK_RST_RINGBUFFER
#define MCU_BLK_RST_RINGBUFFER_Msk              (0x1UL << MCU_BLK_RST_RINGBUFFER_Pos)    ///< Bitmask of MCU_BLK_RST_RINGBUFFER
/**
 * @def   MCU_BLK_RST_RINGBUFFER
 * @brief RINGBUFFER module reset.
 * <pre>
 * @a 1'b0 : Reset
 * @a 1'b1 : Release
 * </pre>
 */
#define MCU_BLK_RST_RINGBUFFER                  MCU_BLK_RST_RINGBUFFER_Msk

#define MCU_BLK_RST_I2C3_Pos                    (14U)    ///< Poision of MCU_BLK_RST_I2C3
#define MCU_BLK_RST_I2C3_Msk                    (0x1UL << MCU_BLK_RST_I2C3_Pos)    ///< Bitmask of MCU_BLK_RST_I2C3
/**
 * @def   MCU_BLK_RST_I2C3
 * @brief I2C3 module reset.
 * <pre>
 * @a 1'b0 : Reset
 * @a 1'b1 : Release
 * </pre>
 */
#define MCU_BLK_RST_I2C3                        MCU_BLK_RST_I2C3_Msk

#define MCU_BLK_RST_ADC_Pos                     (15U)    ///< Poision of MCU_BLK_RST_ADC
#define MCU_BLK_RST_ADC_Msk                     (0x1UL << MCU_BLK_RST_ADC_Pos)    ///< Bitmask of MCU_BLK_RST_ADC
/**
 * @def   MCU_BLK_RST_ADC
 * @brief ADC module reset.
 * <pre>
 * @a 1'b0 : Reset
 * @a 1'b1 : Release
 * </pre>
 */
#define MCU_BLK_RST_ADC                         MCU_BLK_RST_ADC_Msk

#define MCU_BLK_RST_XDAC_Pos                    (16U)    ///< Poision of MCU_BLK_RST_XDAC
#define MCU_BLK_RST_XDAC_Msk                    (0x1UL << MCU_BLK_RST_XDAC_Pos)    ///< Bitmask of MCU_BLK_RST_XDAC
/**
 * @def   MCU_BLK_RST_XDAC
 * @brief XDAC module reset.
 * <pre>
 * @a 1'b0 : Reset
 * @a 1'b1 : Release
 * </pre>
 */
#define MCU_BLK_RST_XDAC                        MCU_BLK_RST_XDAC_Msk

#define MCU_BLK_RST_YDAC_Pos                    (17U)    ///< Poision of MCU_BLK_RST_YDAC
#define MCU_BLK_RST_YDAC_Msk                    (0x1UL << MCU_BLK_RST_YDAC_Pos)    ///< Bitmask of MCU_BLK_RST_YDAC
/**
 * @def   MCU_BLK_RST_YDAC
 * @brief YDAC module reset.
 * <pre>
 * @a 1'b0 : Reset
 * @a 1'b1 : Release
 * </pre>
 */
#define MCU_BLK_RST_YDAC                        MCU_BLK_RST_YDAC_Msk

#define MCU_BLK_RST_AFDAC_Pos                   (18U)    ///< Poision of MCU_BLK_RST_AFDAC
#define MCU_BLK_RST_AFDAC_Msk                   (0x1UL << MCU_BLK_RST_AFDAC_Pos)    ///< Bitmask of MCU_BLK_RST_AFDAC
/**
 * @def   MCU_BLK_RST_AFDAC
 * @brief AFDAC module reset.
 * <pre>
 * @a 1'b0 : Reset
 * @a 1'b1 : Release
 * </pre>
 */
#define MCU_BLK_RST_AFDAC                       MCU_BLK_RST_AFDAC_Msk

#define MCU_BLK_RST_AFC_Pos                     (19U)    ///< Poision of MCU_BLK_RST_AFC
#define MCU_BLK_RST_AFC_Msk                     (0x1UL << MCU_BLK_RST_AFC_Pos)    ///< Bitmask of MCU_BLK_RST_AFC
/**
 * @def   MCU_BLK_RST_AFC
 * @brief AFC module reset.
 * <pre>
 * @a 1'b0 : Reset
 * @a 1'b1 : Release
 * </pre>
 */
#define MCU_BLK_RST_AFC                         MCU_BLK_RST_AFC_Msk

#define MCU_BLK_RST_MISC_Pos                    (20U)    ///< Poision of MCU_BLK_RST_MISC
#define MCU_BLK_RST_MISC_Msk                    (0x1UL << MCU_BLK_RST_MISC_Pos)    ///< Bitmask of MCU_BLK_RST_MISC
/**
 * @def   MCU_BLK_RST_MISC
 * @brief MISC module reset.
 * <pre>
 * @a 1'b0 : Reset
 * @a 1'b1 : Release
 * </pre>
 */
#define MCU_BLK_RST_MISC                        MCU_BLK_RST_MISC_Msk

#define MCU_BLK_RST_PWM_Pos                     (21U)    ///< Poision of MCU_BLK_RST_PWM
#define MCU_BLK_RST_PWM_Msk                     (0x1UL << MCU_BLK_RST_PWM_Pos)    ///< Bitmask of MCU_BLK_RST_PWM
/**
 * @def   MCU_BLK_RST_PWM
 * @brief PWM module reset.
 * <pre>
 * @a 1'b0 : Reset
 * @a 1'b1 : Release
 * </pre>
 */
#define MCU_BLK_RST_PWM                         MCU_BLK_RST_PWM_Msk

#define EFLASH_REMAP_RST_Pos                    (0U)    ///< Poision of EFLASH_REMAP_RST
#define EFLASH_REMAP_RST_Msk                    (0xFFFFFFFFUL << EFLASH_REMAP_RST_Pos)    ///< Bitmask of EFLASH_REMAP_RST
/**
 * @def   EFLASH_REMAP_RST
 * @brief Resets CPU, FMA and eflash
 * <pre>
 * @a 8'hAA55A5A5 : Eflash remap reset and set remap_reset_vld to 1
 * @a Other       : No effect
 * </pre>
 */
#define EFLASH_REMAP_RST                         EFLASH_REMAP_RST_Msk

/** @} RESET_CONTROL_BITMAP */
/** @} RESET_CONTROL */

/**
 * @defgroup CHIP_ID Chip ID Register
 * @ingroup  SYSREG
 * @brief    Chip ID Register
 * @{
 */

/** @} CHIP_ID_REG */


/**
 * @defgroup FUNC_AUXI MCU Functionality Auxiliary Registers
 * @ingroup  SYSREG
 * @brief    MCU Functionality Auxiliary Registers
 * @{
 */

/**
 * @defgroup FUNC_AUXI_BITMAP MCU Functionality Auxiliary Bitmap
 * @ingroup  FUNC_AUXI
 * @brief    Bitmap of MCU Functionality Auxiliary Registers
 * @{
 */
#define MCU_MODE_CTL_MODE_CTL_Pos               (0U)    ///< Poision of MCU_MODE_CTL_MODE_CTL
#define MCU_MODE_CTL_MODE_CTL_Msk               (0x3UL << MCU_MODE_CTL_MODE_CTL_Pos)    ///< Bitmask of MCU_MODE_CTL_MODE_CTL
/**
 * @def   MCU_MODE_CTL_MODE_CTL
 * @brief Mode Control bit for MCU to inform 3@.3v power domain for power down mode.
 */
#define MCU_MODE_CTL_MODE_CTL                   MCU_MODE_CTL_MODE_CTL_Msk

#define MCU_MODE_CTL_EFLASH_REMAP_Pos           (2U)    ///< Poision of MCU_MODE_CTL_EFLASH_REMAP
#define MCU_MODE_CTL_EFLASH_REMAP_Msk           (0x1UL << MCU_MODE_CTL_EFLASH_REMAP_Pos)    ///< Bitmask of MCU_MODE_CTL_EFLASH_REMAP
/**
 * @def   MCU_MODE_CTL_EFLASH_REMAP
 * @brief Eflash remap.
 * <pre>
 * @a 1'b0 : remap.
 * @a 1'b1 : not remap.
 * </pre>
 */
#define MCU_MODE_CTL_EFLASH_REMAP               MCU_MODE_CTL_EFLASH_REMAP_Msk

#define MCU_MODE_CTL_DEBUG_PAUSE_Pos            (3U)    ///< Poision of MCU_MODE_CTL_DEBUG_PAUSE
#define MCU_MODE_CTL_DEBUG_PAUSE_Msk            (0x1UL << MCU_MODE_CTL_DEBUG_PAUSE_Pos)    ///< Bitmask of MCU_MODE_CTL_DEBUG_PAUSE
/**
 * @def   MCU_MODE_CTL_DEBUG_PAUSE
 * @brief Debug pause enable.
 * <pre>
 * @a 1'b0 : enable wdt and timer to pause during debug state
 * @a 1'b1 : wdt and timer continue working in debug state
 * </pre>
 */
#define MCU_MODE_CTL_DEBUG_PAUSE                MCU_MODE_CTL_DEBUG_PAUSE_Msk

#define MCU_MODE_CTL_EXT_INT_1_Pos              (0U)    ///< Poision of MCU_MODE_CTL_EXT_INT_1
#define MCU_MODE_CTL_EXT_INT_1_Msk              (0x3UL << MCU_MODE_CTL_EXT_INT_1_Pos)    ///< Bitmask of MCU_MODE_CTL_EXT_INT_1
/**
 * @def   MCU_MODE_CTL_EXT_INT_1
 * @brief external interrupt 1 trigger mode.
 * <pre>
 * @a 2'b00 : level high trigger
 * @a 2'b01 : level low trigger
 * @a 2'b10 : pulse edge trigger
 * @a 2'b11 : falling edge trigger
 * </pre>
 */
#define MCU_MODE_CTL_EXT_INT_1                  MCU_MODE_CTL_EXT_INT_1_Msk

#define MCU_MODE_CTL_EXT_INT_2_Pos              (2U)    ///< Poision of MCU_MODE_CTL_EXT_INT_2
#define MCU_MODE_CTL_EXT_INT_2_Msk              (0x3UL << MCU_MODE_CTL_EXT_INT_2_Pos)    ///< Bitmask of MCU_MODE_CTL_EXT_INT_2
/**
 * @def   MCU_MODE_CTL_EXT_INT_2
 * @brief external interrupt 2 trigger mode.
 * <pre>
 * @a 2'b00 : level high trigger
 * @a 2'b01 : level low trigger
 * @a 2'b10 : pulse edge trigger
 * @a 2'b11 : falling edge trigger
 * </pre>
 */
#define MCU_MODE_CTL_EXT_INT_2                  MCU_MODE_CTL_EXT_INT_2_Msk

#define DGB_SIG_OEN_CTL_0_Pos                   (0U)    ///< Poision of DGB_SIG_OEN_CTL_0
#define DGB_SIG_OEN_CTL_0_Msk                   (0x1UL << DGB_SIG_OEN_CTL_0_Pos)    ///< Bitmask of DGB_SIG_OEN_CTL_0
/**
 * @def   DGB_SIG_OEN_CTL_0
 * @brief DEBUG SIG[0] OEN
 * <pre>
 * @a 1'b0 : output
 * @a 1'b1 : input
 * </pre>
 */
#define DGB_SIG_OEN_CTL_0                       DGB_SIG_OEN_CTL_0_Msk

#define DGB_SIG_OEN_CTL_1_Pos                   (1U)    ///< Poision of DGB_SIG_OEN_CTL_1
#define DGB_SIG_OEN_CTL_1_Msk                   (0x1UL << DGB_SIG_OEN_CTL_1_Pos)    ///< Bitmask of DGB_SIG_OEN_CTL_1
/**
 * @def   DGB_SIG_OEN_CTL_1
 * @brief DEBUG SIG[1] OEN
 * <pre>
 * @a 1'b0 : output
 * @a 1'b1 : input
 * </pre>
 */
#define DGB_SIG_OEN_CTL_1                       DGB_SIG_OEN_CTL_1_Msk

#define DGB_SIG_OEN_CTL_2_Pos                   (2U)    ///< Poision of DGB_SIG_OEN_CTL_2
#define DGB_SIG_OEN_CTL_2_Msk                   (0x1UL << DGB_SIG_OEN_CTL_2_Pos)    ///< Bitmask of DGB_SIG_OEN_CTL_2
/**
 * @def   DGB_SIG_OEN_CTL_2
 * @brief DEBUG SIG[2] OEN
 * <pre>
 * @a 1'b0 : output
 * @a 1'b1 : input
 * </pre>
 */
#define DGB_SIG_OEN_CTL_2                       DGB_SIG_OEN_CTL_2_Msk

#define DGB_SIG_OEN_CTL_3_Pos                   (3U)    ///< Poision of DGB_SIG_OEN_CTL_3
#define DGB_SIG_OEN_CTL_3_Msk                   (0x1UL << DGB_SIG_OEN_CTL_3_Pos)    ///< Bitmask of DGB_SIG_OEN_CTL_3
/**
 * @def   DGB_SIG_OEN_CTL_3
 * @brief DEBUG SIG[3] OEN
 * <pre>
 * @a 1'b0 : output
 * @a 1'b1 : input
 * </pre>
 */
#define DGB_SIG_OEN_CTL_3                       DGB_SIG_OEN_CTL_3_Msk

#define DGB_SIG_OEN_CTL_4_Pos                   (4U)    ///< Poision of DGB_SIG_OEN_CTL_4
#define DGB_SIG_OEN_CTL_4_Msk                   (0x1UL << DGB_SIG_OEN_CTL_4_Pos)    ///< Bitmask of DGB_SIG_OEN_CTL_4
/**
 * @def   DGB_SIG_OEN_CTL_4
 * @brief DEBUG SIG[4] OEN
 * <pre>
 * @a 1'b0 : output
 * @a 1'b1 : input
 * </pre>
 */
#define DGB_SIG_OEN_CTL_4                       DGB_SIG_OEN_CTL_4_Msk

#define DGB_SIG_OEN_CTL_5_Pos                   (5U)    ///< Poision of DGB_SIG_OEN_CTL_5
#define DGB_SIG_OEN_CTL_5_Msk                   (0x1UL << DGB_SIG_OEN_CTL_5_Pos)    ///< Bitmask of DGB_SIG_OEN_CTL_5
/**
 * @def   DGB_SIG_OEN_CTL_5
 * @brief DEBUG SIG[5] OEN
 * <pre>
 * @a 1'b0 : output
 * @a 1'b1 : input
 * </pre>
 */
#define DGB_SIG_OEN_CTL_5                       DGB_SIG_OEN_CTL_5_Msk

#define DGB_SIG_OEN_CTL_6_Pos                   (6U)    ///< Poision of DGB_SIG_OEN_CTL_6
#define DGB_SIG_OEN_CTL_6_Msk                   (0x1UL << DGB_SIG_OEN_CTL_6_Pos)    ///< Bitmask of DGB_SIG_OEN_CTL_6
/**
 * @def   DGB_SIG_OEN_CTL_6
 * @brief DEBUG SIG[6] OEN
 * <pre>
 * @a 1'b0 : output
 * @a 1'b1 : input
 * </pre>
 */
#define DGB_SIG_OEN_CTL_6                       DGB_SIG_OEN_CTL_6_Msk

#define DGB_SIG_OEN_CTL_7_Pos                   (7U)    ///< Poision of DGB_SIG_OEN_CTL_7
#define DGB_SIG_OEN_CTL_7_Msk                   (0x1UL << DGB_SIG_OEN_CTL_7_Pos)    ///< Bitmask of DGB_SIG_OEN_CTL_7
/**
 * @def   DGB_SIG_OEN_CTL_7
 * @brief DEBUG SIG[7] OEN
 * <pre>
 * @a 1'b0 : output
 * @a 1'b1 : input
 * </pre>
 */
#define DGB_SIG_OEN_CTL_7                       DGB_SIG_OEN_CTL_7_Msk

#define DGB_SIG_OEN_CTL_8_Pos                   (8U)    ///< Poision of DGB_SIG_OEN_CTL_8
#define DGB_SIG_OEN_CTL_8_Msk                   (0x1UL << DGB_SIG_OEN_CTL_8_Pos)    ///< Bitmask of DGB_SIG_OEN_CTL_8
/**
 * @def   DGB_SIG_OEN_CTL_8
 * @brief DEBUG SIG[8] OEN
 * <pre>
 * @a 1'b0 : output
 * @a 1'b1 : input
 * </pre>
 */
#define DGB_SIG_OEN_CTL_8                       DGB_SIG_OEN_CTL_8_Msk

#define DGB_SIG_OEN_CTL_9_Pos                   (9U)    ///< Poision of DGB_SIG_OEN_CTL_9
#define DGB_SIG_OEN_CTL_9_Msk                   (0x1UL << DGB_SIG_OEN_CTL_9_Pos)    ///< Bitmask of DGB_SIG_OEN_CTL_9
/**
 * @def   DGB_SIG_OEN_CTL_9
 * @brief DEBUG SIG[9] OEN
 * <pre>
 * @a 1'b0 : output
 * @a 1'b1 : input
 * </pre>
 */
#define DGB_SIG_OEN_CTL_9                       DGB_SIG_OEN_CTL_9_Msk

#define DGB_SIG_OEN_CTL_10_Pos                  (10U)    ///< Poision of DGB_SIG_OEN_CTL_10
#define DGB_SIG_OEN_CTL_10_Msk                  (0x1UL << DGB_SIG_OEN_CTL_10_Pos)    ///< Bitmask of DGB_SIG_OEN_CTL_10
/**
 * @def   DGB_SIG_OEN_CTL_10
 * @brief DEBUG SIG[10] OEN
 * <pre>
 * @a 1'b0 : output
 * @a 1'b1 : input
 * </pre>
 */
#define DGB_SIG_OEN_CTL_10                      DGB_SIG_OEN_CTL_10_Msk

#define DGB_SIG_OEN_CTL_11_Pos                  (11U)    ///< Poision of DGB_SIG_OEN_CTL_11
#define DGB_SIG_OEN_CTL_11_Msk                  (0x1UL << DGB_SIG_OEN_CTL_11_Pos)    ///< Bitmask of DGB_SIG_OEN_CTL_11
/**
 * @def   DGB_SIG_OEN_CTL_11
 * @brief DEBUG SIG[11] OEN
 * <pre>
 * @a 1'b0 : output
 * @a 1'b1 : input
 * </pre>
 */
#define DGB_SIG_OEN_CTL_11                      DGB_SIG_OEN_CTL_11_Msk

#define DGB_SIG_OEN_CTL_12_Pos                  (12U)    ///< Poision of DGB_SIG_OEN_CTL_12
#define DGB_SIG_OEN_CTL_12_Msk                  (0x1UL << DGB_SIG_OEN_CTL_12_Pos)    ///< Bitmask of DGB_SIG_OEN_CTL_12
/**
 * @def   DGB_SIG_OEN_CTL_12
 * @brief DEBUG SIG[12] OEN
 * <pre>
 * @a 1'b0 : output
 * @a 1'b1 : input
 * </pre>
 */
#define DGB_SIG_OEN_CTL_12                      DGB_SIG_OEN_CTL_12_Msk

#define DGB_SIG_OEN_CTL_13_Pos                  (13U)    ///< Poision of DGB_SIG_OEN_CTL_13
#define DGB_SIG_OEN_CTL_13_Msk                  (0x1UL << DGB_SIG_OEN_CTL_13_Pos)    ///< Bitmask of DGB_SIG_OEN_CTL_13
/**
 * @def   DGB_SIG_OEN_CTL_13
 * @brief DEBUG SIG[13] OEN
 * <pre>
 * @a 1'b0 : output
 * @a 1'b1 : input
 * </pre>
 */
#define DGB_SIG_OEN_CTL_13                      DGB_SIG_OEN_CTL_13_Msk

#define DGB_SIG_OEN_CTL_14_Pos                  (14U)    ///< Poision of DGB_SIG_OEN_CTL_14
#define DGB_SIG_OEN_CTL_14_Msk                  (0x1UL << DGB_SIG_OEN_CTL_14_Pos)    ///< Bitmask of DGB_SIG_OEN_CTL_14
/**
 * @def   DGB_SIG_OEN_CTL_14
 * @brief DEBUG SIG[14] OEN
 * <pre>
 * @a 1'b0 : output
 * @a 1'b1 : input
 * </pre>
 */
#define DGB_SIG_OEN_CTL_14                      DGB_SIG_OEN_CTL_14_Msk

#define DGB_SIG_OEN_CTL_15_Pos                  (15U)    ///< Poision of DGB_SIG_OEN_CTL_15
#define DGB_SIG_OEN_CTL_15_Msk                  (0x1UL << DGB_SIG_OEN_CTL_15_Pos)    ///< Bitmask of DGB_SIG_OEN_CTL_15
/**
 * @def   DGB_SIG_OEN_CTL_15
 * @brief DEBUG SIG[15] OEN
 * <pre>
 * @a 1'b0 : output
 * @a 1'b1 : input
 * </pre>
 */
#define DGB_SIG_OEN_CTL_15                      DGB_SIG_OEN_CTL_15_Msk

#define DGB_SIG_OEN_CTL_16_Pos                  (16U)    ///< Poision of DGB_SIG_OEN_CTL_16
#define DGB_SIG_OEN_CTL_16_Msk                  (0x1UL << DGB_SIG_OEN_CTL_16_Pos)    ///< Bitmask of DGB_SIG_OEN_CTL_16
/**
 * @def   DGB_SIG_OEN_CTL_16
 * @brief DEBUG SIG[16] OEN
 * <pre>
 * @a 1'b0 : output
 * @a 1'b1 : input
 * </pre>
 */
#define DGB_SIG_OEN_CTL_16                      DGB_SIG_OEN_CTL_16_Msk

/** @} FUNC_AUXI_BITMAP */
/** @} FUNC_AUXI */


/**
 * @defgroup RST_STAT MCU Reset Status Register
 * @ingroup  SYSREG
 * @brief    MCU Reset Status Register
 * @{
 */

/**
 * @defgroup RST_STAT_BITMAP MCU Reset Status Bitmap
 * @ingroup  RST_STAT
 * @brief    MCU Reset Status Registers
 * @{
 */

#define RST_STAT_BOOT_STAT_Pos                  (0U)    ///< Poision of RST_STAT_BOOT_STAT
#define RST_STAT_BOOT_STAT_Msk                  (0x3UL << RST_STAT_BOOT_STAT_Pos)    ///< Bitmask of RST_STAT_BOOT_STAT
/**
 * @def   RST_STAT_BOOT_STAT
 * @brief Boot status Register
 * <pre>
 * @a 2'b00 : status after external hardware reset
 * @a 2'b01 : status after watch dog reset
 * @a 2'b10 : status after MCU_SOFT_RST or GLOBAL_SOFT_RST
 * @a 2'b11 : eflash remap reset
 * </pre>
 */
#define RST_STAT_BOOT_STAT                      RST_STAT_BOOT_STAT_Msk

/** @} RST_STAT_BITMAP */
/** @} RST_STAT */

/**
 * @defgroup MCU_AUX_DBG MCU Auxiliary Debug Registers
 * @ingroup  SYSREG
 * @brief    MCU Auxiliary Debug Registers
 * @{
 */

/**
 * @defgroup MCU_AUX_DBG_BITMAP MCU Auxiliary Debug Bitmap
 * @ingroup  MCU_AUX_DBG
 * @brief    Bitmap of MCU Auxiliary Debug Registers
 * @{
 */

#define MCU_AUX_DBG0_Pos                          (0U)    ///< Poision of MCU_AUX_DBG0
#define MCU_AUX_DBG0_Msk                          (0xFFFFFFFFUL << MCU_AUX_DBG0_Pos)    ///< Bitmask of MCU_AUX_DBG0
/**
 * @def   MCU_AUX_DBG0
 * @brief It is an auxiliary register for SW to use for debug information record.
 */
#define MCU_AUX_DBG0                              MCU_AUX_DBG0_Msk

#define MCU_AUX_DBG1_Pos                          (0U)    ///< Poision of MCU_AUX_DBG1
#define MCU_AUX_DBG1_Msk                          (0xFFFFFFFFUL << MCU_AUX_DBG1_Pos)    ///< Bitmask of MCU_AUX_DBG1
/**
 * @def   MCU_AUX_DBG1
 * @brief It is an auxiliary register for SW to use for debug information record.
 */
#define MCU_AUX_DBG1                              MCU_AUX_DBG1_Msk

#define MCU_AUX_DBG2_Pos                          (0U)    ///< Poision of MCU_AUX_DBG2
#define MCU_AUX_DBG2_Msk                          (0xFFFFFFFFUL << MCU_AUX_DBG2_Pos)    ///< Bitmask of MCU_AUX_DBG2
/**
 * @def   MCU_AUX_DBG2
 * @brief It is an auxiliary register for SW to use for debug information record.
 */
#define MCU_AUX_DBG2                              MCU_AUX_DBG2_Msk

/** @} MCU_AUX_DBG_BITMAP*/
/** @} MCU_AUX_DBG*/
/** @} SYSREG */

#ifdef __cplusplus
}
#endif /* __cplusplus */

#endif /* GT98XX_DEVICE_GT9881_SYSCTRL_H_ */
